With recent improvement in signal transmission speed and a recent increase in signal transmission capacity between information processing devices in high-end servers or supercomputers, optical interconnection using a high-speed optical transmission technique in short-range or middle-range signal transmission between CPUs has been studied in order to break a limit of electrical signal transmission. In the optical interconnection, an optical module or the like that converts an electrical signal into an optical signal is employed and data is transmitted between a transmitting-side optical transmission device and a receiving-side optical transmission device using an optical signal via a transmission line such as an array optical fiber. Regarding a signal speed, there is a need for high-speed data communication of, for example, 25 Gb/s so as to cope with wide-band signal transmission between the information processing devices.
In order to satisfactorily transmit and receive digital signals, there is a need for determining each data bit at a correct timing in a receiving-side information processing device. Accordingly, the receiving-side information processing device determines data using timing information for determining a timing at which data is read. As a simple unit that acquires the timing information, there is a method of causing a transmitting-side information processing device to transmit a clock signal in parallel with a data signal.
On the other hand, in recent high-speed data communication such as optical interconnection, since it is difficult to combine a clock timing transmitted in parallel with data due to a transmission delay, transmission of a clock signal in parallel with a data signal is not performed, but a method of embedding clock information in a data signal and causing a receiving-side information processing device to recover a clock is often used. Regeneration of a clock is performed by a clock recovery circuit of the receiving-side information processing device.
A phase-locked loop (PLL) circuit or the like is used in the clock recovery circuit, and the phase-locked loop circuit includes a phase/frequency detector, a loop filter, and a voltage-controlled oscillator (VCO). A clock signal is recovered by adjusting a control voltage of a clock VCO through comparison with a phase of an internal clock signal at data edges which are a rising edge and a falling edge of a received data signal using the phase-locked loop circuit.
A technique of generating an edge pulse in which a rising edge and a falling edge of a reference pulse are delayed by a predetermined time in order to detect data edges of a data signal is known in the related art. In addition, a technique of detecting edges using a NOR circuit or a NAND circuit and an inverter circuit is known in the related art.    Patent Document 1: Japanese Laid-open Patent Publication No. 57-210718    Patent Document 2: Japanese Laid-open Utility Model Publication No. 61-131130    Patent Document 3: Japanese Laid-open Patent Publication No. 06-125251
In a clock recovery circuit using the above-mentioned phase-locked loop circuit, when there is no data edge, phase comparison at that time is not performed and adjustment of a clock signal is not performed. Accordingly, when identical digits succeed as a data signal for a long time, a control voltage of a clock VCO varies and a phase shift, that is, a jitter, of a clock signal occurs. Accordingly, there is a possibility that data will not be determined at a correct timing and a bit error or the like will occur, thereby causing degradation in transmission quality.
Therefore, it is considered that the degradation in transmission quality is reduced by detecting succession of identical digits in an input data signal and stopping the phase-locked loop circuit during the succession of identical digits.
However, in the technique of adding a predetermined delay to an edge pulse or the technique using a NOR circuit or a NAND circuit and an inverter circuit, the succession of identical digits is not detected. Accordingly, it is difficult to reduce the degradation in transmission quality when identical digits succeed in a data signal.